This invention relates to switch mode power converters.
The electronics industry strives to reduce the size and weight of power supplies for its products. One major factor that limits the size or power density of a power supply is its thermal behavior. Increasing the size of the heatsink for the power components can reduce thermal problems, but physical size of the power converter will limit the area of the heatsink that can be used. Alternatively, a smaller heatsink can be used if less heat is generated from the power components. Reducing heat generation is accomplished by increasing efficiency.
Two kinds of power loss are associated with the electronic switch of a switch mode power supply. First is the conduction loss, determined by the resistance of the switch when the switch is on. Second is the switching loss which is caused by the voltage and current overlap during the switching transition (i.e. when the switch turns on or off). The conduction loss can be reduced by choosing a lower resistance switch. However, most low resistance electronic switches, e.g. low resistance MOSFETs, have increased stray capacitance across the switch terminals. The increased stray capacitance causes more switching loss during the switching transition when the stray capacitance discharges into the switch resistance. The usual technique to eliminate this drawback is using zero voltage switching (ZVS).
FIG. 1 is a schematic diagram of a prior art ZVS circuit. The two switches 1, 2 are programmed to turn on alternately. (Switches 1 and 2 cannot be on simultaneously or they will short circuit capacitor 6 across input voltage source 20.) When switch 1 is on, current flows from input voltage source 20, through winding 7 of transformer 30, and through switch 1, thereby causing winding 8 of transformer 30 to deliver power to a load 24 via a filter circuit 26.
When switch 1 is closed, voltage Vin is applied across winding 7. Since transformer 30 is inductive, when switch 1 opens, current through winding 7 cannot change instantaneously, and therefore begins to flow through a loop comprising diode 3 and capacitor 6. During the time in which diode 3 conducts current, switch 2 closes. During the time in which diode 3 conducts and the time in which switch 2 is closed, capacitor 6 is connected across winding 7.
Capacitor 6 provides a substantially constant reset voltage for transformer 30 to prevent transformer 30 from saturating. After switch 2 turns on, voltage across capacitor 6 forces current to flow into winding 7 in a direction A. Switch 2 then turns off, and the energy stored in winding 7 forces the current to change its path and discharge capacitor 5. (Capacitor 5 is the parasitic capacitance inherently present across switch 1.) Energy in capacitor 5 is pumped out of capacitor 5 and back to voltage source 20. After capacitor 5 is fully discharged, current flows through diode 4 so that approximately zero volts are applied across switch 1. Switch 1 then turns on under a ZVS condition. Further information concerning this circuit is shown in U.S. Pat. No. 5,126,931, issued to Jitaru.
To satisfy the ZVS condition for the circuit in FIG. 1, one must provide a) sufficient delay between the time switch 2 opens and the time switch 1 closes, and b) sufficient energy storage in winding 7 to discharge capacitor 5. One must also ensure that switches 1 and 2 are not on simultaneously. Given these constraints, engineers may find the practical design of this circuit difficult. A more simple circuit with fewer design constraints for achieving high efficiency is therefore sought.